;***************************************************************************
;* Copyright (C) 1989 by NCR Corporation    This program		   *
;* contains proprietary and confidential information.  All rights reserved *
;* except as may be permitted by prior written consent.                    *
;*************************************************************************** 

AdapterId 0000h

AdapterName "128K Cache Module"

NumBytes 4

FixedResources	pos[0]=0XXXX0XXb pos[1]=0XXXXXXXb pos[2]=XXXXX00b

NamedItem
	Prompt "128K Cache "
	choice "Enable"		pos[0]=XXXXXX1Xb
	choice "Disable"	pos[0]=XXXXXX0Xb
Help
"Selecting Disable forces all memory read/write cycles to be cache 'misses'."

NamedItem
	Prompt "Wait State Select"
	choice "50 MHz"		pos[0]=X01XXXXXb
	choice "33 MHz"		pos[0]=X00XXXXXb
	choice ">50 Mhz" 	pos[0]=X10XXXXXb
	choice ">> 50 Mhz"	pos[0]=x11XXXXXb
Help
"This option causes the wait state bits to be set to 00,01,10,11 for 
systems with clock speeds of 33,50,>50,>>50, respectively."

NamedItem
	Prompt "Processor Speed Select"
	choice "50 MHz"		pos[0]=XXX0XXXXb
	choice "33 MHz"		pos[0]=XXX1XXXXb
Help
"Choose the appropriate processor configuration for the system."

NamedItem
	Prompt "Cache Type"
	choice "2 Way Set Associative"	pos[0]=XXXX0XXXb
	choice "Direct Mapped"		pos[0]=XXXX1XXXb
Help
"Choose the type of cache to be used in the system."

NamedItem
	Prompt "Combine and Store"
	choice "Disable"	pos[0]=XXXXXXX0b
	choice "Enable"		pos[0]=XXXXXXX1b
Help
"This option allows the 128K Cache to combine multiple writes before
updating memory."

NamedItem
	Prompt "Async/Sync Clock Select"
	choice "Asynchronous"	pos[1]=X1XXXXXXb
	choice "Synchronous"	pos[1]=X0XXXXXXb
Help
"When Synchronous is selected, the 128K Cache assumes that the Microprocessor
and the Processor Bus clocks are synchronized. If this is not the case, select 
Asynchronous to avoid violating the setup and hold times of a Microprocessor
internal register."

NamedItem
	Prompt "Top of Memory"
	choice "4M  "		pos[1]=XX000001b
	choice "8M  "		pos[1]=XX000010b
	choice "12M "		pos[1]=XX000011b
	choice "16M "		pos[1]=XX000100b
	choice "20M "		pos[1]=XX000101b
	choice "24M "		pos[1]=XX000110b
	choice "28M "		pos[1]=XX000111b
	choice "32M "		pos[1]=XX001000b
	choice "36M "		pos[1]=XX001001b
	choice "40M "		pos[1]=XX001010b
	choice "44M "		pos[1]=XX001011b
	choice "48M "		pos[1]=XX001100b
	choice "52M "		pos[1]=XX001101b
	choice "56M "		pos[1]=XX001110b
	choice "60M "		pos[1]=XX001111b
	choice "64M "		pos[1]=XX010000b
	choice "68M "		pos[1]=XX010001b
	choice "72M "		pos[1]=XX010010b
	choice "76M "		pos[1]=XX010011b
	choice "80M "		pos[1]=XX010100b
	choice "84M "		pos[1]=XX010101b
	choice "88M "		pos[1]=XX010110b
	choice "92M "		pos[1]=XX010111b
	choice "96M "		pos[1]=XX011000b
	choice "100M"		pos[1]=XX011001b
	choice "104M "		pos[1]=XX011010b
	choice "108M "		pos[1]=XX011011b
	choice "112M "		pos[1]=XX011100b
	choice "116M "		pos[1]=XX011101b
	choice "120M "		pos[1]=XX011110b
	choice "124M "		pos[1]=XX011111b
	choice "128M"		pos[1]=XX100000b
	choice "132M"		pos[1]=XX100001b
	choice "136M"		pos[1]=XX100010b
	choice "140M"		pos[1]=XX100011b
	choice "144M"		pos[1]=XX100100b
	choice "148M"		pos[1]=XX100101b
	choice "152M"		pos[1]=XX100110b
	choice "160M"		pos[1]=XX101000b
	choice "164M"		pos[1]=XX101001b
	choice "168M"		pos[1]=XX101010b
	choice "176M"		pos[1]=XX101100b
	choice "192M"		pos[1]=XX110000b
	choice "196M"		pos[1]=XX110001b
	choice "200M"		pos[1]=XX110010b
	choice "208M"		pos[1]=XX110100b
	choice "224M"		pos[1]=XX111000b
	choice "256M"		pos[1]=XX111111b
Help
"Choose the proper top of cached memory."

NamedItem
	Prompt "Write Buffer Wait State"
	choice "One Wait State"		pos[2]=XXXX1XXXb
	choice "No Wait State"		pos[2]=XXXX0XXXb
Help
"This option delays certain types of microprocessor write cycles
to the Processor Bus interface by one clock cycle."

NamedItem
	Prompt "Cache Memory Mapped I/O"
	choice "Enable"		pos[2]=XXXXX0XXb
	choice "Disable"	pos[2]=XXXXX1XXb
Help
"This option allows you to Enable/Disable the caching of data 
in the 640K to 1M range."
